Research And Implementation Of SAR ADC For Wideband Wireless Communication System

Compared with the analog signals, the digital signals have many advantages such as strong anti-interference capacity, high transmission quality and easy integration. As the key chip that converts the analog signal to the digital signal, ADC is an important module to achieve digitization.With the use of more digital circuits, SAR ADCs directly benefit from the improvement of the CMOS manufacture process. Therfore,SAR ADCs have the lower power consumption and the smaller area compared with the other ADCs. Moreover, not using operational amplifiers and easily achieving rail-to-rail signal swing, SAR ADCs have been increasingly applied in medium resolution and medium sampling rate systems, and have gotten more and more researches and attentions. Based on the SAR ADCs that are applied in the wideband wireless communication system, this dissertation mainly focuses on the study of high performance, low power and high robustness.The specific research contributions for high performance low power SAR ADC include:1) A FOM-based method is proposed to determine the DAC unit capacitance. With this method, the dissertation researches the effect of the DAC unit capacitance on the SNDR and the power consumption of the SAR ADC.The correlation between the DAC unit capacitance and the FOM of the ADC is further studied. Therefore,the minimum FOM of 17.92 fJ/Conv.-step and the optimal unit capacitance of 1.59 fF are obtained, achieving an optimal tradeoff between the performance and the power consumption of the ADC.2) An improved dynamic preamplifier-latch comparator is proposed. The comparator uses cascode as the bias of the preamplifier and hence increases the output impedance of the bias and the CMRR of the preamplifier. Therefore, the signal-dependent offset caused by the common-mode voltage variation is diminished and the performance of the ADC is improved.The specific research contributions for high performance high robustness SAR ADC include:1) A high-low supply voltage technology is proposed by providing high supply voltage for the comparator and low supply voltage for the other blocks. The high supply voltage further increases the output impedance of the bias of the preamplifier and further improves the CMRR of the preamplifier. So the performance of the SAR ADC is improved. "he other blocks work under the low supply voltage to ensure the low power consumption of the ADC.2) This dissertation proposes a DAC control signal correction latch. With the positive feedback, the latch corrects the error of the DAC control signal that is resulted from mismatch. Therefore, the latch makes the diffierential DAC control signals to be strictly complementary and hence settles the code missing problem caused by mismatch. With the Monte-Carlo mismatch simulated results, the worst SFDR of the ADC is increased by 2 dB by the correction latch, leading to an improved performance of the ADC.3) A comparator clock circuit is proposed. With the data selector, the clock circuit distributes different clock widths for the different bits of the successive approximation procedure. For the two high bits, the narrow clock width is distributed to ensure the sufficient discharge of the DAC capacitor, while for the low eight bits, the wide clock width is distributed to ensure the sufficient comparison of the comparator. With optimized time distribution, each bit of the ADC achieves a good performance.4) At high sample rate, the sum of the mininum sampling time and the minimum comparison time is close to the system clock period. Therefore, this dissertation presents a delay-configurable clock circuit. With 5-bit digital codes, the circuit can configurate 32 scales for the duty cycle of the system clock, achieving different ratios between the sampling time and the comparison time of every system period. The optimal duty cycle can be achieved at different sample rates,different process corners and different temperatures. Therefore, the stability of the ADC is improved.Based on the previous studies, two 55 nm COMS 10-bit 100 MS/s high performance SAR ADCs are designed. Measured results show that the high performance low power SAR ADC achieves a SNDR of 59.8 dB and a SFDR of 70.7 dB. The power consumption and the active area of the ADC are only 1.67 mW and 0.0162 mm2, and the FOM of the ADC is 23.3 fJ/Conv.-step. With measured results,the SNDR and the SFDR of the high performance high robustness SAR ADC are 59.4 dB and 70.5 dB. The ADC consumes 2.1 mW and occupies an area of 0.0188 mm2,resulting in a FOM of 31 fJ/Conv.-step. The 30-point monte-carlo mismatch simulated results show that the worst SNDR and the worst SFDR of the ADC are 56.9 dB and 62.9 dB, respectively. What is more, the SAR ADC achieves good simulation results at -40? ff process corner, 27? tt process corner and 125? ss process corner,ensuring the high robustness of the SAR ADC.