Noc Clock Network And Related Research

As technology scales down , more and more transistors can be integrated in a single chip and the following three problems are getting more and more difficult to be solved. First design productivity gap is boosting .Second ,with the technology scales increasing ,to solve some of the main problems in the deep submicron is more difficult and global synchronization is impossible of being carried out. Thirdly, as more and more transistors can be integrated in a single chip, more IP cores can be integrated in a chip and communication between IP cores become another emphases of design. In order to resolve these problems, reference [1-8] introduces the Network-on-Chip (NoC), which adopts the communication model of the global asynchronous local synchronous (GALS) and regards the communication framework and reusable IP cores as basic to carry out design. NoC alleviates those problems in efficiency and improves the design capacity.The architecture of NoC with the 2-D mesh fabric is sufficiently investigated in the dissertation, which analyzes the ideas of the GALS and introduces the application of GALS in fact. The condition(setup time and hold time )between the clock and register(or other sequential elements)in the synchronous region is studied and the cause of the clock skew and clock jitter is sufficiently discussed and at the same time some methods with resolving them are introduced in the dissertation.Since the requests of the clocks in region and neighbouring regions are different, their clock-distribution networks are not same . Anew mix structure clock -distribution network of the neighbouring region is brought forward , which not only accords with the rules of the application mapping, but also decreases the instantaneous power and increases the communication bandwidth in some extent.A new way that resolves the metastability from design of the system is brought forward in the dissertation aiming at the metastability with communication between different clock region. The metastability only can be generated in the region interfaces by that way. On the base of the fully studying solution of the metastability ,a kind of two clock asynchronous FIFO is designed ,which adopts asynchronous comparing logic and generates the exact sign of the "full" and "empty" by asynchronous set, at the same time adopts synchronizer to solve the metastability .