Research On GALS-Based NoC Router

With the development of single-chip,the traditional on-chip bus-based communication systems is becoming a bottleneck restricting chip processing power,complex structure,low efficiency of data communication are forcing people to research network on chip technology turning.The network-on-chip processing nodes and routing communication interface separation in the design,it is different clock frequencies designed to promote access system modules as possible,so that the globally asynchronous locally synchronous system-on-chip design advantage,but in the asynchronous clock domains room safe,efficient communication becomes a problem on the network design piece.Based on the network-on-chip globally asynchronous locally synchronous paper proposes an improved routing communication model,the use of low-complexity dimension order routing algorithm that can efficiently complete data communications across clock domains,and effectively improve network performance.The use of network-on-chip globally asynchronous locally synchronous characteristics,using a similar concept to calculate the network LAN network on chip synchronous clock frequency resource node aggregation,forming a synchronous clock domains.Because all resource nodes synchronized clock work at the same clock frequency domain,communication is simple,so the use of low complexity in synchronous clock,and efficient routing technology without caching.Between the respective clock domains,using an efficient asynchronous FIFO communication.Data generated by the resource node,if need to pass to the other clock domain,directly use asynchronous FIFO data transfer,data streaming in advance,reaching a logical hierarchical routing results.The paper design safe and efficient asynchronous FIFO,and using double triggers using Gray coding technology to ensure FIFO safe and efficient transfer of data across clock domains.This design not only enables streaming data in advance to avoid congestion,but also save on-chip network storage resources to a large extent,to optimize the performance of the network model.Thesis using Verilog HDL advanced hardware description language on Quartus ? 9.0platform designed chip network communication model,using Modelsim on-chip network communication model made routing functionality and network performance simulation,router as an on-chip network model important core components to complete the data correctly transmission.Finally,the asynchronous FIFO at different depths,network throughputperformance parameters,the average transmission delay,and so do a comparison of the results based on the actual needs of compromise network performance and on-chip storage resource costs.