| As technology scale down, more and more transistors can be integrated in a single chip. Some problems have becomed difficult to be sovled in designing SOC based on chip bus. Firstly, synchronization of global clock is impossible. Secondly, address space is limited. Thirdly, chip bus can not support multi-node parallel communications. Lastly, the bus system is not flexible enough to be expanded. The quantity of IP cores and system performance are restricted due to the problems above. As a consequence, the technology of computer networks was transplanted into SOC design to solve systematic problems of chip bus and this has been the hot topic in research field.The main works of this thesis are as follows. The network adapter module was designed and implemented as IP core to provide a key component of network on chip model. Though studies on the related theories of computer network and requirements of SOC, we proposed a NOC model based on 2D mesh topology, packet switch mode, GALS structure and virtual channels. After that, we gave functional definition of the network adapter module, design and verification programs, data packet format definitions, sub-modules division scheme and circuit details. Besides that, the problems and solutions about GALS interface circuit based on standard cells dynamic memory allocation, synchronizer and ping-pang accessing mechanism of double buffer were highlighted in the paper.The process of the circuit element modeling, synthesis, routing and placement were completed by QuartussII. The process of constructing the test-bench and verification were completed by Modelsim. Performance analysis and verification results show that our network adapter module impement data packaging, asynchronous packet-switch and packet decomposation functions. Speed, packet delay, data throughput, costs and other properties of adapter met the requirements of SOC. Completion of the subject established the foundation for network model and promoted process of network on chip. |
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