Research On SoC And Design Of Interface Circuit Based On GALS Technology

With the development of IC technology and the emergence of IP core reusing, chips of SoC have been gradually becoming the mainstream in the design technology since the latter half of the 20th century. Because of the characteristic size unceasingly reducing with the system complexity increasing, a sole clock or other global signal can't control the clock skew in the ideal scope. At the same time, in order to synchronize signals to the unified clock, the system will consume more powers than it really needs. In this situation, the thought of asynchronous design is regarded.It's difficult to make completely a complicated SoC asynchronous due to be short of EDA tool recently. Thought of GALS was developed in this situation. It implemented communication between asynchronous modules based on asynchronous interfaces. In fact, GALS is a transition from synchronism to asynchronism.This paper started with the main problems of the SoC system, analyzed the limitations of synchronous design, and discussed the advantages of the asynchronous technology in low power loss, non-clockskew, high-speed, modularization and so on. To the technical level of the current SoC design, it proposed the problems of asynchronous technology which may exist in practice.Moreover, this paper introduced asynchronous design principle in detail as well as typical signal models of the circuit level in the asynchronous system, and discussed the theory issue on the asynchronous interface design. It also studied thoroughly the handshake protocol, basing on which to realize the asynchronous interface design. Through the fundamental studying, this paper summarized a brand-new method of asynchronous handshake interface design, which based on memory and state machine. This method was used in GALS, and it used the synchronous designs flow to realize asynchronous design function. The realization was quite simple and it had better technology migration potential. With the Verilog HDL description language and Quartus II 5.0 which is the FPGA development platform, asynchronous FIR filter interface based on 4-phase boundled-data handshaking and asynchronous CORDIC algorithm interface based on 2-phase boundled-data handshaking were designed by this method. Through simulation as well as the result analysis, it was feasible.In addition, this paper also proposed one method for asynchronous FIFO design. It used the handshaking signal to synchronize the address of the FIFO. This design proposal was completed and confirmed in QuartusII 5.0 .The result indicated that, this plan had the unique superiority on the address number absoluteness.