Design And Implenmentation Of A 2.5Gbps CMOS Monolithic 16:1 Multiplexer

Optic-Fiber communication systems based on Synchronous Digital Hierarchy (SDH) have been remarkably progressed to support the rapid development of information technology and multimedia service. As a critical high-speed module in electro-optic interface, multiplexers (MUX) used to be designed in GaAs, bipolar Si or BiCMOS technology. With the continuous decreasing of CMOS feature size, it has been possible to realize Gbps circuits in CMOS technology.A monolithic 2.5 Gbps 16:1 Multiplexer in a 0.25μm CMOS technology is presented to make application easier. The monolithic MUX can be used in STM-16 multiplexing system, which consists of 16:1 Parallel-In-Serial-Out (PISO) and 2.5 GHz clock multiplier unit (CMU). 16 bit 156Mbps parallel inputs are serialized into a 2.5 Gbps serial output by 16:1 PISO. Data retimer is included to reduce duty-cycle distortion and output jitter. The clock multiplier unit, which is based on phase-locked loops (PLLs) generates 2.5 GHz clock from external 156MHz reference clock to supply PISO and data retimer. This paper gives a thorough analysis of the phase noise in PLLs using SpectreRF and Matlab/Simulink. The Electro-Static Discharge (ESD) protection circuits are adopted in the chip according to the whole-chip ESD planning in order to improve the reliability.As a mixed-signal system, the layout design of the MUX is essential to the ultimate performance. The techniques such as guard ring, decoupling and shielding are adopted in order to reduce the interference among digital and analog circuits. After fabrication, the on-wafer measurements exhibit that the MUX works stably at 2.5 Gbps and consumes 330 mW from a 2.5 V power supply. The measured phase noise of the CMU is -90.9 dBc/Hz at 10 kHz offset, and the root-mean-squared jitter is 10 ps. The MUX operates up to 3.2 Gbps with a 2.5V power supply, while the maximal output frequency of the CMU is 4.2 GHz.