Chip Design Verification And Validation Process

Today large-scale chips are used wildly. It's always reported that bugs of chips lead to great lost due to the inefficiency of verification. The correctness of each chip should be taken into the first consideration. Appling modern verification technologies and reformatting verification flow will capture more bugs, which will raise quality of chip designs. This dissertation focuses on the verification technology and quality management in chip designs especially in ASIC designs.Verification technologies are cataloged into dynamic verification technology, which must run DUV, and static verification technology, which needn't run DUV. Dynamic verification, stand stone of verification, will continue acting as an important role during the verification flow in the future. With the rapid development recent years the static verification can offer relative faster speed and shorter time than dynamic one can do in the growing field of large scale chip. The dynamic verification and the static verification will depend on each other in the coming verification field.Another focus for verification technology is hardware technology. By building an physical module of DUV to turn the sequential execution of software simulation into consequential execution of hardware emulation, emulation technology can ran on 100 to 1000 times speed than simulation technology does, which erase the bottleneck of simulation technology. But there still are some technology problems such as max speed, scale, and interface to software, for emulation technology to overcome.Advanced verification languages start to make their contribution today when the verification technology has been a specialize one. Verification languages offer powerful language platform for verification engineers. They can focus on the expression of verification thought other than the one of language details by using verification languages other than hardware description languages to build verification environment. The wildly use of verification languages will raise the efficiency and quality of design verification.One key to guarantee design quality is developing verification technologies, another important one is scientific quality management.Based on theory study and practice, the individual verification principle is obeyed by the whole industry. The individual verification is necessary for verification takes different viewpoints and tools. And the individual verification makes quality management more possible. Total quality management acts as traffic rules in design flow. The kernel of quality management is to guarantee the product quality by guaranteeing the product flow quality.During the digital video post-processing project adapting scientific verification flow we apply verification theory and skills, which makes satisfied quality of design.