ASIC Design And Implementation Of LDPC Encoder Chip

Low-density parity-check(LDPC)code is a kind of linear grouping code with a sparse check matrix.It not only has excellent characteristics near the Shannon limit but also has less complexity and flexible structure.Therefore,it has become the focus of research and development in channel coding in recent years.At present,with the development of integrated circuit field,LDPC encoder chip with small volume,high speed,low power consumption,and low cost will have strong market competitiveness.For the(8176,7154)LDPC codes under the CCSDS standard,this thesis conducts RTL code design,logic synthesis,formal verification,and back-end layout design of the LDPC encoder chip.The specific contents include: designing RTL code of encoding circuit,simulating and board-level verification;Logical synthesis and formal verification of RTL codes are carried out.Path delay is greatly reduced by timing optimization,and dynamic power consumption of the chip is reduced by inserting a gated clock and multi-threshold voltage.The netlist generated by logic synthesis is designed with backend implementation,iterative optimization of timing ang P?R,DRC and LVS checks are also performed on the P?R results.In the code design stage,based on fully mastering the coding principle,according to the characteristics of the generation matrix,the shift register is used for storage to design the core logic circuit of coding calculation.Then,use Verilog language to write the RTL code,and the code is simulated and verified at the board level.The Design Compiler is used to complete the logic synthesis of the LDPC encoder chip.Based on completing the synthesis steps,the method of inserting a gated clock and multi threshold voltage technology is adopted in the optimization stage,which greatly reduces the dynamic power consumption of the chip and the internal power consumption of the unit,and correspondingly reduces the chip area.Compare the netlist file generated by logic synthesis with RTL code with Formality,and confirm that the generated netlist file is correct in logic function.Innovus is used to complete the backend layout design of the LDPC encoder.In addition to completing the basic operations with design reading,floorplan,place,clock tree synthesis,and routing,it also optimizes the chip timing,area,and routing resources to a certain extent by optimizing the layout of the LDPC encoder chip,and optimizes the power routing strategy through high-level routing and setting different linewidth,to reduce the voltage drop and power consumption of power line.In addition,in the clock tree synthesis,the delay and skew of the clock tree are reduced by resetting the clock signal routing rules and inserting the gated clock.After the routing is completed,Tempus is used to analyze and optimize the timing of the layout,repair the timing violations,and compare the reports before and after repair.This LDPC encoder chip is based on the advanced ASIC(Application Specific Intergrated Circuit)design and verification platform,and uses 180 nm technology to design the back-end layout of LDPC encoder.The back-end design results of the LDPC encoder chip show that the working frequency of the chip is 200 MHz,the scale is 594000 logic gates,and the layout area is 3mm × 3mm.After physical verification such as design rule check and layout versus schematic consistency check,the LDPC coding chip designed in this paper can meet the tape-out standard.