Automatic Functional Verification Of The Multi-protocols Processing Chip Bashed On SpecmanE

With the rapid development of ASIC and their function to be more complex, the integrated circuits may contain up to several hundred million transistors. For chip design, verification must be an important part of the design process from the beginning, along with synthesis, system software and debug strategies. Up to 70% of the overall design effort is taken due to verification. Verification, especially functional verification has become the number one bottleneck in the design process and reducing functional verification time is crucial to project success. Traditional functional verification method is hard to make verification scenarios and cover corner cases. So, new functional verification methodology and techniques are needed. High-level Verification Languages (HVLs) have emerged to solve the functional verification bottleneck.Cadence's E is one of the most modern languages designed specially for verification. Currently, Specman Elite by Cadence Design, Inc. is the only tool that supports E. Main characteristics includes object-oriented programming, coverage-driven functional verification, reusable verification components, and automatic generation, checking and coverage.The high-speed router and the Ethernet-switch can process multiple protocols. With the booming of the scale and complexity of IC design, the ASIC to process multiple protocols has appeared. In this thesis, the verification of multiple-protocol-processing chip, as example, is presented and how to make automatic functional verification is demonstrated.Through the project, we can conclude that automatic functional verification with Specman E may improve the efficiency of verification.