Research And Design The Chip Verification Platform Based On Sdh

In the development of ASIC, the quality of verification decides the success rate of tapout. Along with the high-speed progress of microelectronics technology, ASIC becomes increasingly complex; the workload of verification also increases. Therefore, improving efficiency and the standard of verification are key factors to improve the chip’s quality. The SDH Framer achieves lOGbps of line processing functions which include handling both upstream and downstream directions’pointers, overheads and alarms; some maintainability and testability functions are also involved. Considering the complexity of this chip, in order to insure fully validated and guarantee zero flaw of the design with in a limited time, the most appropriate and efficient verification method must be adopted. The main work of the dissertation can be summarized as following aspects:1. Based on the agreements of SDH and the features of the SDH Framer, a verification strategy is planned.2. System Verilog (SV) is applied as the language of verification environment. And its advanced technologies are used to design verification environment and its components.3. Considering SV’s drawbacks as a compiled language, Tcl is adopted as the language of test case (TC). This dissertation also uses automated scripts to submit TCs in batches and automatically checks operation results, so that the verification time can be reduced and the efficiency of verification improved.4. In the clock module unit testing, comparing with the traditional clock-verification method, an improved method is used to ensure the quality of the clock module design.5. Both upward and downward of SDH Framer’s basic business are verified in this dissertation, which guarantees the subsequent verification work.6. The verification of overhead serial is taken as a typical example to the entire chip’s functional verification; also some analytical tools to the problems and the results of the verification are introduced. The chip that developed by this project has successfully taped out. It indicates that the verification platform has good effects on the functional verification of SDH chip. The platform not only improved the verification enffciency, ensured the success of the chip, but also its high automation reduced the workload of the verification staff. At the same time, the flexibility and reusability of the verification platform makes it a common verification platform for SDH chip.