Dvb-c Receiver Chip Design And Implementation Of Data Synchronization,

Digital High Definition Television (HDTV) utilizes several most advanced practical technologies in the world,such as advanced compression coding technologies and audio & video technologies. It is representative of the third generation television,and will have an important influence on the lives of people in the future. This thesis deals with the algorithm of synchronization and its DVB-C (Digital Vision Broadcasting - Cable) implementation. The synchronization is used in the DVB receiver of HDTV Cable Broadcasting Transmission System.The main contents of this thesis are at a glance:Chapter 1 serves as an introduction to the subject. After an overview of Digital HDTV,DVB-C system is discussed in detail. EDA design method is also introduced at last.Chapter 2 discusses the principle of synchronization. The emphasis is placed on the analysis of timing loop based on interpolation.Chapter 3 treats the design of the timing synchronization loop. At first,it introduces the method of loop parameters,including gain of phase detecting,gain of loop filter and frequency sensitivity,then simulations are done under different structures and parameters. According to the results of simulation,loop structure is decided.Chapter 4 illuminates the ASIC project of synchronization. In the same time,the flow of ASIC front-end design is introduced;it also lists some skills and ideas in the work.The main contributions of this paper are proposing the algorithm and realization of synchronization in DVB-C,and calculating the technical parameters of synchronization loop.