Study On The Key Techniques And Applications Of HDTV Demodulator

When stepping into the digital era, the information exchange among people becomes more and more popular. As a high band-efficiency digital modulation scheme, OFDM(Orthogonal Frequency Division Multiplex) is widely adopted in the wide-band communication area, such as Wireless LAN, Enhanced 3G, HDTV, UWB and so on. Related specification or standards are IEEE802.11, TD-SCDMA, DVB-T proposed by ETSI, DTMB proposed by China etc.In recent years, with the great progress made in the field of IC and digital communication, it is possible to integrate the whole high-speed digital communication system in a single chip. OFDM includes TDS-OFDM, COFDM and ZP-OFDM. Because of its fast and accurate synchronization, high spectrum efficiency and low implementation complexity TDS-OFDM has become one of the most important OFDM transmission schemes. Therefore the design and VLSI architecture of TDS-OFDM demodulator has become the focus of academic and industrial research. This paper tries to solve the common difficulties in the VLSI design of various DTV demodulators. The researching of the key techniques for DTV can be used in many wide-band OFDM communications, such as DVB-T, DVB-H, DTMB, HDTV receiver and so on.The main contribution of this dissertation can be concluded as following.1. Based on the study of various existing standards related to wide-band OFDM communication, this work analyse the main impacts on HDTV demodulator. Then the basic architecture for TDS-OFDM demodulator is discussed, as well as the main issues during its chip design.2. Study on the problems of OFDM synchronization thoroughly, including carrier synchronization, timing synchronization, and frame synchronization technology. Based on the analysis of the OFDM system which is influenced by synchronization offset, these work emphases the energy on the analysis of SNR loss. With deep study of the existed OFDM synchronization algorithm and the characteristic of PN sequence, according to the digital communication technology, this work proposes the synchronization algorithm and architecture based on OFDM transmitting system with PN sequence as guard interval. The proposed scheme significantly improves the synchronization performance and reduces the chip complexity.3. According to the analysis of wireless channel, channel estimator and equalizer are very important. For COFDM, a novel equalizer architecture that includes a two-dimensional interpolation estimation unit and an equalization unit is propsed and a combined pilot and data channel estimation algorithm based on EM COFDM is proposed. For TDS-OFDM, a brief overview of the existing TDS-OFDM channel estimation and equalization schemes is given. Based on this, a cyclic-correlation based channel estimator is implemented. Implementation results demonstrate that more than 8000 clock cycles and 50% design complexity reduction can be achieved without loss BER performance compared to FFT-based method. The effect of phase noise in OFDM system is also discussed and a novel five point algorithm based on TPS for the phase noise suppression is proposed, which reduces the requirement to tuner quality and the system cost.4. This work delivers a through study on the long code rate irregular LDPC VLSI architecture. Choose the min-sum algorithm from the exiting LDPC decoder algorithms according to its characteristics. A new method to control memories is proposed, which can reuse memories for the different code rates only by increasing little memory usage.5. According to the DTMB syterm, this work proposes the performance metric for HDTV demodulator and discusses the relationship between key module and certain performance metric. Parts of the algorithm and VLSI architectures are used in DTMB demodulator chip design. The FPGA verification and MPW ASIC implementation results indicate the performance of the proposed algorithms and architectures.