Dvb-h Cyclic Code Of The Algorithm And Asic Realization

Digital High Definition Television (Digital HDTV), as the third era Television Standard, has become the focus of contest in the countries all over the world. It will affect the world's politics, economy and culture greatly. This thesis focuses on the principles of the BCH code (error protection of TPS) and RS code (for MPE-FEC) and implementation in ASIC of DVB-H (Digital Vision Broadcasting - Handheld) channel receiver.The thesis consists of five chapters.The first chapter gives an overview of digital TV, introduces the cocept of ASIC and SOC.The second chapter treats of several new technologies in DVB-H, especially the MPE-FEC frame structure. Simultaneously, it sketches the structure of the main parts of DVB-T channel sender and receiver, introduces the principles of OFDM.The research on the theory of cyclic codes and the description of channel model of wireless mobile channel of DVB-H is in chapter three.The rest of the thesis is organized as follows. Chapter four and chapter five present the VLSI designs for BCH(67,53) code and RS(255,191) code in DVB-H. In chapter four, the known Berlekamp-Massey decoding procedure for BCH code is modified to be suitable for hardware implementation. The adder, multiplier and inversion on Galois Field are analyzed respectively in detail also. The chapter five is devoted to the realization of time domain RS decoder based on the "modified Euclid - Chien - Forney" algorithm, which permits efficient pipeline processing with reduced circuitry. This chapter also includes the error indication, the probability of missed alarm and erasure correction of RS code in DVB-H.The main contributions of this thesis are proposing the algorithm and implementation on ASIC of BCH code and RS code in DVB-H system, especially for the design and implementation of RS decoder, compares some Galois Field algorithm and their implementation, also probes into the MPE-FEC frame structure and the erasure correction algorithm of RS code in DVB-H.