| This paper will give a discussion of the method of ASIC design and analysis the HDTV integrated source decoder with embedded RISC core and a improved de-interlacing algorithm for ASIC design.This dissertation introduces the flow of ASIC design and SOC. The principles,characteristics,function,system structure and design flow of synthesis will be described in detail. The structure of the HDL plays a important role in ASIC design since it may not allow tool to meet the designer-specified constraints. Its startpoint for synthesis affects the quality of results after synthesis,thus,to attain good startpoint,some coding styles will be presented.In order to achieve high resolution of image quality,HDTV is developed from analogy television. HDTV video decoder is a key component of high definition television receiver. As audio compression standard of ATSC-HDTV,Dolby AC-3 is a high-quality,low-complexity multichannel audio coder which is used for more and more applications.In this paper,the decoding flow of AC-3 is analyzed,moreover,optimization for software and hardware of decoding of audio. ACS real-time decoding will be archieved with IP-based embedded RISC core by adding special instructions,such as getbits,max,min and adding hardware for the operation of NOP and the optimization of the program.With the variety of service form of HDTV,seeking for low power and miniaturization of consumer electronics presently and the requirement of TFT-LCD replacing CRT,the research of de-interlace is closely bound up HDTV.The key of de-interlace is good interpolation for interlaced video signal. In this paper,de-interlacing algorithm for ASIC digital-TV is analyzed,deferent kinds of de-interlacing algorithm for motion-estimation are introduced,the characteristic of 3-D recursive searching block-matching motion estimation algorithm is reviewed in detail,also the object-based motion estimation algorithm is simplified,which helps to obtain the achievement of lower computation and less hardware. |
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