| With the increasing use of Phase-Locked Loops (PLLs) and Delay-Locked Loops (DLLs) embedded in FPGAs, ASICs, and System-On-Chip (SOC), there is a growing need for methods to verify their operation. This dissertation is a study of the ways in which the testing and verification can be accomplished. It deals with the two main difficulties encountered by any method intended to test an embedded loop: the lack of access and the sensitivity of the circuit. Even though a PLL and a DLL function differently and use different means to provide the adjustments necessary to control the system, they have similar testing requirements. Therefore, they can be tested in like ways as long as the test methods are not dependent on their unique characteristics. This objective is approached in two stages. First a framework is developed for organizing the tests, then a particular test is chosen for further improvement and implementation.; To deal with the ad hoc nature of existing tests, the first task was to create a framework for tests based on the important characteristics of the loops. This framework takes the form of a general and organized list that includes tests for lock, jitter, stability, and modulation response. The main objective of the tests was to analyze the loop without actually measuring the control voltage, because that point is so sensitive that any interference would easily modify the operation of the loop.; From the framework, the step response test was chosen for further improvement. The DLL was selected as the subject of the test because of its simplicity. Both the choices of method and of DUT were influenced by the planned use of a simulator for this portion of the research. After these decisions had been made, the research actually evolved towards an approach that operated in a way that was able to circumvent the complexities created by the original objective of not monitoring the control voltage. (Abstract shortened by UMI.)... |
