Research On Attenuators And Phase-Locked Loops For Silicon-Based Phased Array Systems

The phased array is a multi-antenna array technique that controls the direction of the trans-mitted/received electromagnetic beams through electronic techniques.This technique draws great attention from the applications of military,space research,astronomy and so forth,for its advantages of strong anti-interference capability,high signal-to-noise ratio,fast response speed and so on.With the fast development of the integrated circuits manufacture process,the phased array technique has been part of people's life at fields like transportation,commu-nication,medical treatment,weather,etc.A phased array system is a sophisticated system which consists of digital,analog and microwave sub-systems.Each of these sub-systems affects the performance of overall system even their functions.Thus,researches on the key techniques in phased array systems are critical.The gain control technique is mainly used in the radio frequency front of phased array systems,and its typical implementation is the attenuator,which adjusts the amplitude/power of the transmitted and received signal.The phase locked technique is another crucial technique in phased array systems and has multiple functions,which is utilized not only for the local oscillation but also for the clock generation for digital-analog interfaces and digital processing modules.It is,therefore,of great value for researches on how to take full advantage of the best potential of these two techniques.For the gain controlling,there have been many works published overseas about attenuators on silicon processes.The main home research is based on GaAs process,and the research on silicon-based attenuators is still under the simulation verification.For the phase locked technique,the main researches are on the fractional-N phase locked loops(PLLs).One of the hot topics is to reduce the quantization noise without reducing the loop bandwidth.Current works can be sorted into two categories,analog and digital approaches.The former one can realize perfect quantization noise compensation in theory,but it suffers from the sensitivity to the process,voltage and temperature(PVT).By contract,the later one is robust,but its efficiency is limited to high frequency offsets.In this dissertation,the research is focus on attenuators for gain controlling in phased ar-ray systems and the digital-circuits-based quantization noise suppression techniques for fractional-N PLLs.The main work is as follow:Firstly,lumped and distributed attenuators are modeled and analyzed based on the analysis of the parameters and topologies,and models of silicon switched transistors,on-chip inductors and on-chip transmission lines,and an approach,in which different switch configurations are used in the reference path and attenuation path respectively,and the inductor-based insertion phase compensation technique are proposed for reducing the insertion loss and insertion phase as well as improving the linearity.To verifying the proposed techniques,a lumped attenuator with 5-10 GHz bandwidth is implemented on 0.18-?m RF CMOS process.The core area of this attenuator is 0.55 mm2.The measured insertion loss and the root mean square(RMS)insertion phase are less than 8.3 dB and 9.1°,respectively,and the simulated 1-dB compression point is 18.4 dBm.To further reduce insertion loss,insertion phase and hardware cost and enlarge bandwidth,an attenuator architecture is proposed mixing the ?-,the bridged-T-and the simplified-T topologies,where the the simplified-T topology is used for small-attenuation modules and the other two topologies are used for large-attenuation modules.To test this architecture,a lumped attenuator with 5-20 GHz bandwidth is im-plemented on 0.18-?m RF CMOS process.The core area of this attenuator is 0.43 mm2.The measured insertion loss and the RMS insertion phase are less than 10.8 dB and 12.2°,respectively,and the simulated 1-dB compression point is 15.6 dBm.Compared with pub-lished works,these two attenuators have better performance on insertion loss,hardware cost and linearity.Secondly,a variable-gain semi-distributed attenuator architecture is proposed combining the advantages of lumped attenuators on larger attenuation and low hardware cost with the merits of distributed attenuators on low insertion loss and low insertion phase.In combi-nation with the EM-circuit co-simulation technique,an attenuator architecture with 5-14.5 GHz bandwidth is implemented with 0.18-?m RF CMOS process.The measurement results show that the maximum attenuation range is 32.52 dB and the attenuation step varies among from 1.02 dB to 1.05 dB without affecting the overall performance of the attenuator.In addition,the RMS attenuation amplitude and the RMS insertion phase is 0.84 dB and 7.4°,respectively,and the core area of this attenuator is 0.78 mm2.The overall performance of the attenuator is good,and the attenuation range is wider than the published distributed and semi-distributed attenuators.Additionally,the attenuation step is adjustable.Thirdly,a novel mostly-digital space-time averaging technique is proposed for quantization noise suppression in fractional-N PLLs.In this technique,the multi-channel structure and a vector divider is leveraged to realize the instantaneous fractional division with only sin-gle VCO phase.Theoretically,the noise floor of the quantization noise can be lowered by log10 M(dB)at entire frequency range with M channels.Additionally,the mismatch shap-ing technique is utilized in this technique addressing the mismatch issue in the multi-channel structure.Finally,to verify the proposed quantization noise suppression technique,a ?? fractional-N PLL with the loop bandwidth of 1 MHz(1/20 fref)and output frequency of 1 GHz is implemented on 0.13-?m RF CMOS process,where the number of channels is 8.The post-layout simulation results indicates that the proposed space-time averaging fractional division technique does not affect the loop dynamics and shows that the quantization noise floor is lowered down by 18 dB,which performs much better than the conventional fractional-N PLLs and mostly-digital quantization noise suppression techniques.In this dissertation,the gain control technique is studied based on attenuators,and the quan-tization noise suppression technique for fractional-N PLLs is also studied.The measurement results of attenuators and the simulation result of the PLL show advanced achievements and the application value of this dissertation.This paves ways for the implementation and the application of high-performance attenuators and PLLs.