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Keyword [Phase-Locked Loops (PLL)]
Result: 1 - 8 | Page: 1 of 1
1.
The Clock Processing Chips Design Of 10-40gbit/S Sdh/Sonet,10-Gigabit And Gigabit Ethernet
2.
Design And Implementation Of Debugging Structure Of An X Microprocessor
3.
Based On Noise Analysis Of The Charge Pump Phase-locked Loop Design
4.
C-band Frequency Synthesizer Developed
5.
.10-40gb / S Optical Communication And Gigabit Ethernet Clock Generation And Recovery Circuit Design
6.
The Study On C Band Fine Resolution Low Phase Noise And Spur Frequency Synthesizer
7.
The Design Of480MHz Phase Locked Loop For USB2.0
8.
Injection Locked Synchronous Oscillators (SOs) and Reference Injected Phase-Locked Loops (PLL-RIs
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