Current and delay estimation in deep sub-micrometer CMOS logic circuits

The continual shrinking of CMOS device features raises some problems; one of the most relevant is signal propagation delay estimation. Using the circuit simulator is prohibitively time consuming. Faster, yet, accurate delay estimation methods are strongly needed. The propagation delay is affected by MOSFET current and capacitance, the applied signal slope and the number of serially connected MOSFETs.; This work proposes an extended MOSFET saturation current model for deep submicrometer technologies by adding the channel-length modulation effects. Moreover, the thesis proposes four classes of MOSFET capacitance models. These classes differ in the number of parameters they use to characterize MOSFET capacitances. In addition, the work adopts one more MOSFET capacitance class from the literature that recognizes the difference between the capacitances associated with a rising transition and those associated with falling transition.; Furthermore, the dissertation proposes four delay model levels that are related to the MOSFET capacitance classes. Also, two more delay levels are adopted from the literature: one that is based on logical effort technique and a more complicated one that is based on Shams model. Shams model is modified to give two more delay model levels. One of them uses a simpler way of accounting for the effect of serially-connected MOSFETs. The other one uses a more complicated expression for the input slope effect. An empirical technique to estimate the linear and quadratic effects of the input signal slope on the delay is also proposed.; The study is performed on 0.13 mum and 90 nm CMOS technologies to demonstrate how much complexity and details are required for reasonably accurate delay estimation.