| Analog to digital converter is necessary to any circuit system which needs to obtain signal from the nature. It is a bridge between analog and digital signal, and is usually used in various aspects of industrial production or scientific research. The successive approximation analog-to-digital converter(SAR-ADC), with moderate accuracy and speed, low cost and low power consumption advantages, widely used in industrial control, medical instrument, portable equipment, military reconnaissance, etc.. Along with the larger scale CMOS circuit, and the decrease of transistor inherent gain, SAR ADC becomes more and more popular.This thesis focuses on medium speed and precision successive approximation analog to digital converter. Starting from the basic principles and structure of SAR ADC, the author makes comparative analysis of the characteristics of different modules, and completes the design of each module in terms of several aspects such as: speed, accuracy and low-power. The final structure adopts capacitive digital-analog convertor(CDAC) structure with unit bridge capacitance. The whole capacity of CDAC is 5.75 pF. To reduce the power during the 0-1 conversion of DAC,the author designs a module to check and avoid 0-1conversion using two reference voltage. The new circuit`s power is 20% less than the traditional CDAC. Taking speed and power consumption into consideration, this circuit uses two-level dynamic voltage comparator. This structure can be shut down when it is not required, which solves the contradiction between gain and setting time. The setting time is 5ns, and offset is 400 uV. Digital logic circuit, which is made of 24 triggers, completes the search algorithm and the latch function.For the physical implementation, the author completes the analysis, design and simulation of a 10 b, 350 kHz successive approximation analog to digital converter in CSMC 0.5 CMOS process. The overall power consumption of SAR ADC is 0.61 mW. The finally layout area of the SAR ADC is. |
PDF Full Text Request