Research And Design Of All-digital Delay-locked Loop Based On FPGA

With the rapid development of ultra-large-scale integrated circuits,the degree of digitization is getting higher and higher,and the speed of data processing is getting faster and faster.For digital circuits,the precise operation of digital information processing,including operation,transmission,and storage,needs to be guaranteed by a stable clock,whether it is synchronous or non-synchronous.In highly integrated FPGAs,the distribution of on-chip clocks becomes more and more important.Clock delay and clock skew seriously affect system performance.The delayed phase-locked loop,as the core part of the FPGA clock network,can not only reduce the clock skew,but also provide a series of functions for the system clock synchronization and lock,fully meet the FPGA timing requirements.All-digital delay-locked loops are based on traditional phase-locked loops.The traditional delay-locked loop adopts analog circuit design,its phase-locked skew is large,the lock phase range is very narrow,and the structure is complex and the stability is poor,which is easily affected by temperature.After analyzing these,we believe that the fully digital design can effectively improve these defects.In order to improve theperformance of FPGA chip,reduce the clock delay,reduce the clock skew,increase the lock range,and increase the lock speed,this paper designs a fully digital delay-locked loop based on FPGA.In the design of the all-digital delay-locked loop,the system unit is designed in a modular manner.The system is mainly composed of a double D flip-flop type phase frequency detector,a frequency measurement module,a phase measurement module,and a phase adjustment module,and the delay unit is analyzed.The phase measurement module converts the value obtained by the phase detector into a delay number,and then the phase adjustment module adjusts the delay chain according to the number of stages.The delay chain is divided into coarse and fine adjustment,and the controller adjusts the delay according to the number of stages.When fine tuning is divided into four levels,it can be adjusted several times,greatly speeding up the locking speed.The simulation of each module and the entire system was verified.It fully proves that the all-digital structure operates stably and does not accumulate phase errors.The all-digital delay phase-locked loop circuit designed in this paper can realize phase lock fast,not only can effectively eliminate the clock propagation delay,has a wide range of lock,but also has a high phase lock accuracy,simple structure,suitable for A variety of applications such as microprocessors,memory and IC design.