Research And Design Of Low-power Frequency Synthesizer With Adaptive Frequency Calibration

With the development of wireless communication technology, various short range wireless standards such as wireless local area networks, Bluetooth and ZigBee have been defined and implemented. The chips with lower power and lower costs become the key technology in wireless system. On the other hand, the higher and higher demands of radio frequency transceiver front-end are proposed. Frequency synthesizer is the key block of a radio frequency transceiver, which supplies local oscillation signals. This thesis focuses on the study and design of low-power and low-noise frequency synthesizers.With development of the CMOS integrated circuits and scaling down size, the increase of fT makes the frequency of CMOS RF circuits increasing higher. However the noise and power have been problems of RF circuit design because of the decrease of supply voltage, increase of leakage and noise of device.To solve these problems, firstly, the thesis discusses the frequency synthesizer’s architectures and specifications, and analyzes phase noise, locking time, power consumption and so on, expounds the influence of each module to the system and the optimizing. Secondly, analysis and design of frequency synthesizer is presented in detail: a digital controlled capacitor array and low-pass filter techniques have been adopted in VCO to optimal the noise on the basis of analysis of the VCO’s architectures and noise. Later on, an in-depth discussion about the constructions of high-speed prescaler is done and the Injection-Locked Frequency Divider is adopted in order to reduce power consumption at the premise of the enough divide frequency scope (reached to 79%); then a low-power, high-speed Charge Pump is designed and the optimization for reducing the in-band noise is done; moreover, based on a brief analysis of the adaptive frequency calibration(AFC) techniques, a high-frequency-resolution and high-speed AFC system is proposed. Finally, through optimization of noise, power of each module and the loop bandwidth, an integer-N frequency synthesizer is implemented in a SMIC0.13um RF CMOS process. The range of frequency is 2.1-2.1 GHz, exhibiting phase noise of-97dBc/Hz、-106dBc/Hz and-113dBc/Hz at 10 KHz,100 KHz、1MHz and the power consumption is 2.12mA.