Design And Area Optimization Of Large Capacity EFuse Based On 40nm CMOS Technology

With the rapid development of semiconductor technology, the production cost of the chip is increasing, which makes us the improvement of the yield about the chip is more crucial. Meanwhile, in the new process node, the deviation of production process and the deviation of device’s simulation model are more likely to cause the parameter deviations of the circuits. Thereby a fuse technology was introduced, we can use the fuses to replace the failures circuits by redundancy circuits of chip for improving yield, we can also rebuild the circuit structure for getting some new functions and fine tune some parameters of the circuits (TRIM). But the traditional fuse technology is not compatible with the mainstream CMOS technology, so that the cost is high. So the emerging eFuse with small size, low cost and programmable after packaging has became a study hotspot of this field.This thesis summarizes the eFuse current research status firstly, and then we started this study from selecting the eFuse type, then we has designed a parallel input and parallel output eFuse IP, with4K bits of the eFuse unit basing on the SMIC standard40nm low leakage CMOS process. Finally, the designed eFuse was taped out, manufactured and tested successfully, the test result can meet the spec, of design.The eFuse size for IP is very strict, so we went on to optimize the size of eFuse in next chapter, which can save about thirty percent IP size of high density eFuse IP after improvement. The size optimization is significantly.