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Design Of A 2.4GHz WLAN Power Amplifier Based-on 40nm CMOS Process

Posted on:2021-03-05Degree:MasterType:Thesis
Country:ChinaCandidate:C Y YangFull Text:PDF
GTID:2518306476460294Subject:Master of Engineering
Abstract/Summary:PDF Full Text Request
In the past few years,as consumer demand for wireless products has increased,wireless local area network technology has gradually matured.In order to achieve a higher data transmission rate,the wireless local area network uses orthogonal frequency division multiplexing technology for signal modulation,which has a very high peak-to-average ratio.Therefore,as the core component of the wireless front-end of the wireless local area network,the power amplifier requires a high degree of linearity to maintain signal integrity.At the same time,power amplifiers,as the most power-consuming modules in RF systems,need to achieve as high efficiency as possible to increase the service life of the equipment.Therefore,designing a CMOS power amplifier for wireless local area network has good research significance and engineering value.This thesis is based on a 40nm CMOS process and is designed for a 2.4GHz power amplifier for wireless local area network.The power amplifier is based on a differential cascode architecture and includes four parts:an amplifier circuit,an input matching network,an on-chip balun and a bias circuit.The amplifying circuit adopts multiple gated transistors structure,which is composed of a main amplifier and an auxiliary amplifier.The main amplifier is biased in class AB and the auxiliary amplifier is biased in class C,so as to achieve third-order nonlinearity cancellation and improve linearity.The bias circuit uses a resistor and transistor voltage divider network to compensate for the effect of process angle deviation on the circuit.The input matching network uses an LC matching.The on-chip balun is used to complete the output impedance conversion,and the conversion from differential to single-ended is achieved at the same time.The post-simulation results show that when the working frequency band is 2.4?2.4835GHz and the power supply voltage is 3.3V,the input matching degree S11is-11.17d B,the output 1d B gain compression point is 23.27d Bm,the saturation power is 28.54d Bm,the power gain is 20.06d B,and the maximum power additional efficiency is 38.93%.All the indicators of this paper meet the design requirements.After taped and verified,it can be used in 2.4GHz WLAN transceiver system chip.
Keywords/Search Tags:Power amplifier, 40nm CMOS, WLAN, MGTR
PDF Full Text Request
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