The 100GHz Divide-by-2 Frequency Divider Design Based On 40nm CMOS Technology

In recent years,with the vigorous development of the fifth generation mobile communication(5G)technology and the continuous improvement of people's demand for high-speed and short-range communication,millimeter-wave(30?300GHz)has become a hot band for researchers in the industry because of its rich spectrum resources and short wavelength.CMOS technology has a broad application prospect because of its advantages of high integration,low cost,mature technology and integration with baseband circuits.More and more millimeter-wave chips based on CMOS process have been designed.As the core module of wireless transceiver,frequency synthesizer directly influences the performance of the whole transceiver system.The core modules of PLL system are voltage controlled oscillator and frequency divider which work at the highest frequency of the system.Their performance,such as operating frequency,tuning range,phase noise and power consumption,will directly determine whether the PLL system and the whole transceiver can work normally.Therefore,based on 40 nm CMOS technology,two 100 GHz frequency dividers applied in millimeter-wave PLL are designed in this thesis.First,a LC frequency divider circuit based on injection locking is designed.In this thesis,several injection locking models and their locking ranges are analyzed in detail.Two injection modes(direct injection and tail current injection)are introduced,and the key performance indexes of the divider are analyzed.On this basis,a direct injection LC type frequency divider is designed,and a common source differential amplifier circuit is designed.Based on the basic structure of traditional direct injection type ILFD,some improvements are made as follows: single end injection is replaced by double end injection,injection tube plus substrate bias,and reasonable selection of related MOS transistor parameters,so as to improve the working frequency,expand the injection locking frequency range and reduce power consumption.The pre-simulation verifies the frequency division function of the circuit.Due to the high working frequency of the frequency divider,the passive component model provided in the process library is not accurate.Therefore,it is necessary to design the corresponding key passive component inductance by electromagnetic field simulation software.Based on the detailed introduction of some rules to be considered in layout and routing,the layout of the circuit is designed and optimized to reduce parasitic,interference and mismatch.After physical verification,the parasitic parameters of the circuit are extracted.Firstly,the parasitic resistance and capacitance of the core MOS transistor and its wiring part are extracted separately,and then the parasitic resistance and capacitance extracted from each node are substituted into the original schematic diagram for corresponding post simulation.Then the parasitic inductance and mutual inductance of the key long wiring part and pad part of the circuit input and output are extracted and replaced into the original circuit for post simulation.The post simulation of the circuit is carried out under different simulation conditions.The results show that under the worst condition(SS process angle,125?),the correct frequency division range is 92GHz?106GHz.The power consumption of the core circuit is 14.9mW with a 0.9 supply voltage.The area of the core circuit is61 ? m×131 ? m.High frequency,wide lock-in range and low power consumption are realized successfully.Then a static current-mode logic divider based on D flip flop is designed.Based on the analysis and comparison of several structures of current-mode logic frequency divider,a static structure divider is designed.In order to broaden the bandwidth of the circuit,inductor parallel-peaking is adopted.By reasonably setting the free oscillation frequency point of the circuit,reasonably designing the inductance and selecting the type and size of MOS transistor,the working frequency of the circuit is increased and the locking range is expanded.The whole circuit with buffer are pre simulated to verify the frequency division function of the circuit.Similarly,the passive inductor is designed by ourselves.The layout of the circuit is designed based on the considerations of layout and avoidance of parasitic effect.After the parasitic parameters of the core circuit and the key input and output lines are extracted,the post simulation of the circuit under various simulation conditions is carried out.The results show that the correct frequency division range of the circuit is 72 ?110GHz under the worst condition(SS process angle,125 ?).The corresponding input sensitivity curve and circuit power consumption curve are given.The power consumption of the core circuit is 25.6 mW with a 1.8 supply voltage.The area of the core circuit is 86 ?m × 150 ?m.The frequency division range is 72?110 GHz with the 300 mV signal input.Finally,the test scheme of the two circuits and the performance comparison of the two circuits are given.