Fpga Cad Back-end Process Research

Compared with ASICs, the most significant characteristic of FPGAs is their flexible programmability, which helps in achieving a short design cycle and no Non-Recurring Engineering (NRE) costs, as well as a reduced time to market. With these advantages, FPGAs are increasingly used in the applications where previously was an exclusive territory of ASICs. Along with fast development of the semiconduc-tor process, modern FPGAs contain many new logic cells and more complicated routing structure, which increase the difficulties of FPGA CAD tools a lot. This paper will focus on the FPGA CAD backend flow, including proposing a unified backend framework, an improved placement algorithm that supports the heterogeneous logic cells, a flexible and fast algorithm for constructing routing resource graph and a single event upsets emulation system.According to different optimized goals, we can have different types of backend flows, such as timing-driven, power-driven, anti-SEU-driven and etc. Moreover, in order to evaluate the efficiency and quality of a given algorithm such as the algorithm used to build routing resource graph or the algorithm used for timing engine, these modules in the backend flow are required to have the flexibility to be replaced with another one. Therefore, a unified backend framework is proposed to facilitate the flexibility and maintainability to the greatest extend.Even the newest version of VPR cannot provide fully support for the heteroge-neous logic cells introduced in the modern FPGAs. This paper aims at solving this problem by modeling each logic cell as a swap object and defining neat rules to im-plement the moving between heterogeneous logic cells. Especially for carry chains, a specific data structure and corresponding algorithm are introduced to improve the ef-ficiency of this placement algorithm.Routing Resource Graph is the key of the routing module. Therefore, this paper proposes a novel algorithm for constructing routing resource graph, aiming at provid-ing fully support for the new kinds of routing resource built in the modern FPGAs. Meanwhile, this proposed algorithm is markedly accelerated by average 60% with multi-thread programming techniques.Experimental results of timing-driven placement and routing implemented ac-cording to the unified framework and the algorithms discussed above show average 16.30% timing improvement compared to non-timing-driven flow for ITC'99 bench-marks.Finally, this paper also presents a hardware-independent weight-based fault in-jection model for accurate emulation of the single event upsets in the SRAM-based FPGAs. Fault injection emulation platform based on JTAG boundary scan and partial run-time reconfiguration is also proposed. Experimental results show that fault injec-tion system composed of both the software model and the hardware platform can achieve more accurate, more efficient and lower cost emulation.