A Fault-tolerant Computing And Communication Verification Platform Based On FPGA

Field Programmable Gate Array(FPGA) is widely applied to the aerospace field with the advantages of high integration density, programmability and so on. The commonly used anti-fuse FPGAs which have the problems of long development cost and long development period, are gradually displaced by the Static Random Access Memory(SRAM) FPGAs. This type of FPGAs has high intergration density, low cost and is dynamically reconfigurable. However, the SRAM-based FPGAs are based on the volatile memories. This structure is inherently sensitive to single event effects, in the radiation environment, which limits their application. Single event upset(SEU) in the memory of SRAM-based FPGA may change the designed circuit structure completely, resulting in the system failure. In order to improve the possibility of applications based on SRAM-based FPGAs in the radiation environment, it is becoming a hot research about how to evaluate single event effect on design of the circuit on the FPGAs.Firstly, based on the basic structural characteristics of SRAM-based FPGAs and the influence of single event upset on SRAM-based FPGAs, this thesis builds a fault-tolerant computing and communication verification platform based on Virtex Series FPGAs. The platform consists of the control unit, the fault-injection testing unit and the reference unit. The control unit is the control center of the entire platform, taking responsible for implementing the fault injection, results collection and so on. The fault-injection testing unit is responsible for testing the circuit design on the FPGAs with the fault injection of single event upset. The reference unit takes the charge of providing the correct result of the same circuit design. The platform can complete the tests to evaluate design sensitivity to single event upset quickly, using the "sequential traversal" way, which can verify the feasibility of the fault tolerance technologies which are implemented for reliable communication and computing algorithms.The implementation of this platform includes the design of hardware and software. In the end of the thesis, the FPGA design of variable node processing unit in low density parity check decoder is chose. The fault injection testing platform is used to test the sensitive position in the design. Test results show that, this testing platform for fault injection is effective.