Research On Reconfigurable Fault-tolerant Structure Of SRAM Type FPGA

SRAM-based FPGAs are sensitive to working environments such as radiation or ionization,In the case of high reliability requirements,fault-tolerant techniques must be applied to ensure the proper operation of the system.Redundancy is a common approach for improving reliability.Triple Modular Redundancy is the most commonly used hardware redundancy technology.However,this kind of static fault-tolerant design method is too expensive,so this paper presents a fault-tolerant method for SRAM-based FPGA by using dynamic reconfiguration technology.The main contents are as follows:(1)This method adjusts the degree of redundancy of the system depending on the various soft error rate.When the error rate is low,the system adopts duplication with compare which has lower area overhead and power consumption.If the soft error rate is high,the system switches to the TMR to eliminate the effects of a single error.By taking the representative circuits in ISCAS'85 benchmark as redundant modules,this paper explains the implementation of reconfigurable fault-tolerant by using Proxy Logic and EAPR technology.Finally,the paper compares the simulation results with the static fault tolerant technique and thus validates the advantages of the proposed method in the aspects of area and power consumption.(2)For further reducing the power consumption caused by redundancy,this paper presents an approximate adder structure and performs its performance verification by using low byte error,which does not affect the performance of some digital systems.So this paper verified the performances of approximate adder.Afterwards,puts forward the reconfigurable fault-tolerant structure based on approximate adder.In this paper,DCT/IDCT transform is taken as an example to illustrate the structure and performance of approximate computation.The method is to do DCT transform to image,then to reconstruct the image by IDCT.By analyzing the quality of image restoration and the hardware resource cost and power consumption,the performance of accurate adder and approximate adder are compared,and the overall performance of the proposed random approximation adder structure is verified.After completion of the simulation verification,the random approximation adder is used to replace the accurate adder.And then several random approximation adder with different numbers of bits are constructed,which can be dynamically called according to the need of fault tolerance by self-reconfiguration of FPGA.