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Design And Implementation Of Seu Fault Injection Platform Based On Partial Reconfiguration Of FPGA

Posted on:2020-05-01Degree:MasterType:Thesis
Country:ChinaCandidate:R S HanFull Text:PDF
GTID:2518306131462214Subject:Electronics and Communications Engineering
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Because of its low cost,high density,high performance and flexible configurability,SRAM-based FPGAs are widely used in aerospace,communications and other fields.Compared with other types of programmable logic devices,SRAM-based FPGAs are more vulnerable to space energetic particles,especially the single Event Upsets(SEUs).Therefore,it is necessary to evaluate the SEU-tolerant performance of SRAM-based FPGAs when used in high reliability scenarios,especially in space radiation environments such as aerospace.In this paper,a SEU fault injection and test platform is implemented by using partial reconfiguration technology of FPGAs and ICAP(Internal Configuration Access Port)in Zynq 7000 series chips.Compared with other fault injection methods,the fault injection method adopted in this paper is highly consistent with the actual operation scenario.On the other hand,the method does not need additional hardware,has less time overhead,and also has high controllability and high observability.The platform can implement fast and low-cost tests of the anti-SEU performance of models running on SRAM-based FPGAs.This paper introduces the principle of SEU fault injection for SRAM-based FPGAs through ICAP bus,and shows the structure of SEU fault injection test platform and the flow of fault-injection test.Then,the above platform is used to do SEU fault injection test on user memory(UM)and configuration memory(CM)of Viterbi decoder and Turbo decoder using LOG-MAP algorithm.The validity of the platform is fully verified by the fault injection test of Viterbi decoder and Turbo decoder.Moreover,both Viterbi decoder and Turbo decoder are widely used in the field of wireless communication and have capabilities of fault-tolerance and error-correction.Therefore,SEU fault-injection test of these two decoders will evaluate the anti-SEU performance of the decoders,and will provide more information,which is indispensable for SEU hardening of Viterbi and Turbo decoders.
Keywords/Search Tags:SRAM-based FPGAs, Fault Injection, Partial Reconfiguration, SEU, Viterbi Decoder, Turbo Decoder
PDF Full Text Request
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