Research Of SRAM-based FPGA Single Event Upset Fault Injection System

SRAM-based FPGA devices are becoming more and more popular in space applications,due to its high density,low cost and the peculiar advantage of dynamic reconfiguration. But in the space radiation environment, SRAM-based FPGAs compared with other types of programmable logic devices, such as the ASICs and Antifuse-based FPGAs are more vulnerable to the single event effects, especially the single event upsets (SEU). In the filed of SEU hardening and testing, foreign institutes and colleges have comparatively mature theoretical and testing experience. But because the related technologies blockade, test conditions and resources restrictions, domestic studies in this field late start, and are in exploring stage. How to estimate SEU effectively and exploit SEU hardening technique has become an urgent problem to be solved.By using partial reconfiguration of Virtex FPGA, this paper realizes a XCV300 / BQV300 fault injection tool. This tool can be used to simulate and test SEU. First, this paper studies SEE of SRAM-based FPGA, particularly the generating mechanism and hardening technology of SEU, and proposes the method of using fault injection to test and simulate SEU. Secondly, according to the storage structure of SRAM-based FPGA this paper demonstrates the feasibility of the scheme which using fault injection technology to flip FPGA configuration memory bits to simulation SEU. On this basis, this paper discusses the fault injection scheme. Again, based on the SelectMAP partial reconfiguration of Virtex FPGA, expound the hardware and software implementation of fault injection tool. Finally, by using the fault injection system to test FPGA typical design, get into the test circuit SEU sensitive bits, and verifies the effectiveness of this test system.