SEU Fault-injection System Design Of SRAM-based FPGA

With rapid development of electronic industry, FPGA is used widely in digitalsystem design and ASIC prototype front-end design because of its high performanceand flexibility. In space field, SRAM-based FPGAs are gradually instead of trad i-tional anti-fuse FPGAs which can’t be programmed more and are expensive. ButSRAM-based FPGAs are inherently sensitive to single event, which limits their a p-plication. It is becoming a hot research about how to evaluate single event effect ofSRAM-based FPGA and how to radiation-harden.Based on the research of configuration memory and configuration structure ofSRAM-based FPGAs, we find that if the frame data in FPGA configuration file is0/1inverted, the configuration memory will be artific ially flipped correspondingly.Single event upset effect can be simulated by this method in FPGA, which becomesthe theory basis for fault injection of SRAM-based FPGA. Based on the theory, thepaper designs a fault injection system of SRAM-based FPGA.Fault injection system in the paper is based on partial reconfiguration technol-ogy. It makes full use of EDK, which is the development tool of Xilinx Inc. Har d-ware part of the system is composed of PowerPC microprocessor, external me mory,ICAP and IP core. The IP core is customized with the unit und er test. ICAP is aninternal port provided by the Xilinx FPGA which can read and write configurationmemory directly. Software part of the system realizes the fault injection processbased on partial reconfiguration technology. One fault is injected using aread-modify-write mechanis m of ICAP. Fault injection results are got by the co m-parison between the test results after fault injection and the golden running results.In the end of the paper, three typical designs of FPGA are chose. Use the faultinjection system to test these designs. And then these designs which are hardenedby three modular redundancy are tested again. Fault injection system is verified e f-fective ly.