.10-bit 50-ms / S Low-power Pipelined Adc Design

This thesis presents the design of a low power 3.3V 50MS/s 10-bit pipelined ADC. Techniques for designing a low power ADC are discussed, and factors limiting the performance of ADC are analyzed. The schematic details and simulation performance are listed.The ADC achieves low power dissipation by using SHA-less architecture and opamp-sharing technique. The first stage with 1-bit-per-stage architecture, replacing the SHA, achieves half signal swing while SNR still remains the same. The reduction of the signal swing allows relatively lower DC gain and bandwidth of op-amp; it also relaxes the requirement of capacitor matching. Four op-amps are used in the design due to sharing technique, which reduces the power consumption by more than 1/3. Scaling down of the size of capacitors and op-amps reduces the power consumption further.High DC-gain and high speed gain-boosting telescopic cascode OTA is adopted in this design to achieve higher resolution and higher linearity. The gate-voltage bootstrapped switch is used in the input sampling network to allow a wideband input signal with excellent linearity. The adopted dynamic comparator with less offset reduces static power dissipation. The optimization in layout design, such as matching the two sampling paths in the first stage, ensures the resolution.Implemented with 0.35μm 2P4M CMOS process, the ADC dissipates 33 mW with a supply voltage of 3.3 V and occupies 2.2 mm2 active areas, the simulated SFDR is 80.27 dB, SNDR is 61.17 dB for an input frequency of 5 MHz at sampling rate of 50 MS/s. And with an input frequency of 25 MHz, SFDR is 79.49 dB, SNDR is 60.75 dB.