Low-voltage Low-power Cmos Pipelined Adc And Implementation

As required by system-on-a-chip(SoC) integration and state-of-the-art CMOS technology, analog supply voltage is forced to decrease, following that of digital part. Meanwhile, handset equipments impose stringent requirement on power consumption. Therefore, low-voltage low-power analog circuits draw more and more attention. The progress of CMOS technology gives rise to both opportunities and challenges to analog circuits. Inherent frequency of MOSFETs is increased with scaling down of the feature size. On the contrary, the inherent gain degradation and low supply voltage significantly challenge to analog circuits. As the bridge between analog domain and digital domain, analog-to-digital converter (ADC) is the indispensable part of SoC.The work focuses on the low-power low-voltage pipelined ADC. Novel architecture is proposed. Four chips are designed and measured. The specific contributions of this work include1 A novel pipelined ADC architecture suitable for sub-IV design is proposed. The architecture relaxes the output swing requirement of op amp in MDAC.2 A novel op amp topology is proposed to eliminate the op amp input offset voltage in successive op amp sharing architecture.3 An improvement has been made to reduce power of the SHA removing pipelined ADC.4 A closed-loop bandwidth model of MDAC is proposed for power optimization.