Radio Frequency Transmitter Module Research And Design

Transmitter and frequency synthesizer, as two indispensable parts of the wireless transceiver, are of the vital importance in wireless communication. This thesis focuses on the study and design of RF frontend circuit, clock-generator for 802.11a and analog baseband for WCDMA/GSM transmitter.The thesis consists of four parts. At the beginning of all, system level design, including the quantitative analysis for individual part on the total behavior, the significance of the clock generator and the linearity of the RF frontend, is described for 802.11a transmitter. Then the clock generator is analyzed and designed. High frequency wide band voltage controlled oscillator, method to alleviate dynamic mismatch and static mismatch for the charge pump circuit, simulation method for the reference spur and the total phase noise are of the main content in the second part. The analog baseband is realized for WCDMA/GSM transmitter, in whom dual-mode variable gain low pass filter is adapted to achieve the circuits'reuse and the 1dB precision gain adjustment is also achived.The above mentioned designs are verified by silicon:the VCO works between 8.64G to 11.62GHz, the integrated phase noise is-33dBc with the reference spur of-76dBc. The spot phase noise is-85dBc/Hz at 100-kHz offset and-116dBc/Hz at 1MHz offset, respectively, which can meet the requirement of the design specifications. The test results of the analog baseband shows that the circuits work well with 3dB bandwidth of 2.7MHz, the gain can be adjust between OdB to-24dB with 1dB step for WCDMA mode, and 3dB bandwidth of 300kHz, OdB to-8dB gain adjustment with 1 dB step for GSM mode.