Design Of A High-speed Cppll For Clock Recovery Circuits

With the development of semiconductor technology,the working frequency of microprocessor gets higher and higher. In order to eliminate the asynchronism between external reference clock and internal clock,and provide a clock of higher frequency for the internal circuits, we need to design high-performance PLL for synchronization and frequency synthesis. As an essential circuit module of modern communication system,PLL has been widely used in clock recovery circuits and frequency synthesizers.This paper describes the design process of a charge pump PLL for clock recovery system.First, we briefly introduced the historical background and research status of PLL,and analyzed the mathematical model of every basic module,according to the basic composition principle of PLL. Then,we give a detailed analysis of the linear model of the system and the design process of every module. Finally, we give the analysis of designed circuit and simulation results.In this design, we used a PFD circuit which contains only 16 MOS transistors and works fast without dead zone.We used a modified CP circuit to suppress charge injection and clock feedthrough effects. A second-order passive low-pass filter is used as loop filter.This design is based on the TSMC 0.35um 2P4M CMOS process and simulation tool is the Hspice software. Simulation results show that with a 3.3V power supply,the output signal frequency is 1.25GHz when the input signal frequency is 625MHz,and the lock time is 200ns,which has met the design requirements.