Design considerations for high-speed clock and data recovery circuits

Design considerations for high speed clock and data recovery circuits are presented. Linear and bang-bang clock recovery architectures are examined and it is shown that the performance of the circuits is related to the performance of the flipflops used to build them. The design of high speed, emitter-coupled logic flipflops is investigated and two flipflops operating at speeds of up to 17GHz and 44GHz in simulation are designed in an experimental SiGe process. The design of voltage-controlled ring oscillators for use in clock recovery circuits is also investigated and an oscillator is designed and fabricated in a 0.18 μm CMOS process. The measured centre frequency of the oscillator is 1.43GHz and the phase noise is −80.2dBc/Hz at a 1MHz offset.