The Design Of 1.8ghz Cmos Integer-n Frequency Synthesizer

The rapidly growing wireless communication market has driven the research and the development of the wireless transceivers at lower cost,lower power consumption and smaller die sizes. As the progress of CMOS and Bi-CMOS technology, most RF component in wireless transceiver, such as low noise amplifier,Mixer,Loop Filter and frequency synthesizer has been to be integrated. The frequency synthesizer, which is usually formed by a Phase-Locked Loop (PLL), is a major and critical component of a wireless transceiver because it provides several clean, stable and programmable local oscillator (LO) signals to RF system. Frequency synthesizer consumes a very large portion of the total power consumption because it operates at the high frequency of the wireless transceiver system and it will determine the whole performances of the RF system.This thesis analyzes the design of the loop parameters and the design method of each block in the frequency synthesizer based on system and circuit level respectively with the"Top-Down"procedure. A third order integer-N frequency synthesizer which implemented in SMIC 0.18um CMOS RF technology is taken as an example.First, from the aspect of system design, the loop parameter design method of the frequency synthesizer is obtained through the analysis of s-domain of open loop. Base on the design flow, loop parameters which meet the system stability can be figured out and a Simulink behavior simulation model is also given to verify it.Second, this thesis briefly introduces the fundamental theory of oscillators and oscillator's class. All kinds of the circuit structures of narrow-band,wide-band are presented. Because the phase noise characteristic of the VCO restricts the quality of the communication system, so academy is paying much attention to it in recent years. After studying two widely used phase noise model: the linear time invariant model (lesson's model) and the linear phase time varying model, we can get the theory foundation of designing the low phase noise VCO.Third, Physical processes of phase noise in differential LC oscillators is analyzed in detail. Four practical methods of lowering phase noise: tail current size opitimization, capacitor filter, switched capacitor array and LC filtering technique are summarized on the base of understanding the functions of the MOS cross coupled pairs and tail current source in the LC VCO.In the end, according to above conclusion, a 1.8GHz central frequency integer-N frequency synthesizer, whose reference frequency is 10MHz, is implemented in SMIC 0.18um CMOS RF technology. A low phase noise LC VCO covering the frequency range from 1.6GHz to 2.1GHz is obtained. Cadence spectreRF simulation result shows that its phase noise has 6dB improvement with the help of three phase noise optimization method. When the center frequency is 1.8GHz, the VCO phase noise simulation result is -104dBc/Hz@100kHz, -127dBc/Hz@1MHz. The no ideal phenomenon of PFD and charge pump which can cause the reference spur of the frequency synthesizer is analyzed and the non-dead zone PFD and high current match charge pump circuit which use the rail-to-rail operation amplifier are also designed. The random divide ratio can be get with the help of designing the dual-modulus prescaler, programmable P counter and S counter exactly. The whole frequency synthesizer can locked in the 10us and the power consumption is 40mW. The whole layout size is 1.5mm~2*2 mm~2.