Research On Key Techniques Of DTC Based Fractional SPLL

With the rapid development of wireless communication technology and the continuous improvement of data traffic,higher performance is required for the frequency synthesizer.Therefore,in recent years,new-type high performance phase-locked loops such as SSPLL,ADPLL,BBPLL,and SPLL have become the research hotspot,and the application of DTC to new-type phase-locked loops makes it exhibit better performance.This thesis will research the key technology of DTC-based fractional SPLL,which focuses on programmable integer frequency divider and DTC control and calibration module.First,this thesis introduces the fundamental principle of fractional SPLL,and analyzes the function and principle of the main module in detail.Meanwhile a linear model of the loop is established,which derives the transfer function of the loop.Then,the loop stability and noise model are analyzed,as well as the influence of the delta-sigma modulator noise on the loop and the method of delta-sigma noise eliminating.Besides the system structure of the DTC-based fractional SPLL is given in the thesis.Finally,the design of the programmable integer frequency divider and DTC control and calibration module is completely designed.The programmable integer frequency divider adopts a structure based on a 2/3 frequency divider,which is composed of a 2/3 frequency divider chain and a stepwise retiming module.In order to increase the operating frequency of the 2/3 frequency divider chain,the first stage 2/3 frequency divider with the highest operating frequency adopts the CML structure,and the remaining stages adopt the improved C~2MOS structure.The application of the stepwise retiming module makes the frequency divider delay fixed at any frequency division ratio,which improveing the linearity and noise performance of the frequency divider,and avoiding the occurrence of metastable phenomena.The DTC control and calibration module mainly includes three parts:delta-sigma modulator,digital control and calibration,and threshold self-calibration comparator.The module realizes the generation of DTC control words,and calibrates the gain error of DTC applying the LMS algorithm,as a result the quantization noise is canceled.The programmable integer frequency divider and the DTC control and calibration module are achieved using the 65nm RF CMOS process.The design uses a combination of semi-custom and full customization design methods.Finally,the layout area of the programmable integer divider module is 0.58mm×0.6mm,and the area of the DTC control and calibration module is 0.2mm×0.17mm.The worst-case of post-simulation results indicate that the working frequency range of the programmable integer divider is 2GHz?14GHz,the frequency division ratio range is 128?255,and the total current consumption is 1.8m A,which meets the requirements.The DTC control and calibration module can work normally in the environment with a frequency up to 100MHz,the gain calibration accuracy is less than 1%,and the average operating current is less than 0.8m A.The decimal SPLL based on DTC has been taped out,and the test plan is given in the thesis,which needs to be verified.