Research Of Key Techniques In 25GHz Phase-Locked Loop

Phase-locked loops(PLL)are used more and more widely in many areas.In transceiver,PLL plays a role as frequency synthesizer and people utilize the frequency synthesizers to generate the clean carrier for mixer.As a result,the frequency synthesizer are commonly required to exhibit an excellent phase noise performance.Based on the proposed methods in this dissertation,a high performance frequency synthesizer is presented.In the research of loop filter(LPF),the design methods of loop filter are demonstrated.The noise transfer functions in frequency synthesizer are analyzed.The noise of CP is studied in integer-N mode and fractional-N mode,respectively.In fractional-N mode,we propose a new analytical method to analyze the the noise from the common-mode feedback(CMFB)circuits.In the research of high speed divider,we proposed a graphical analytical method for CML-DFF divider.The analytical model facilitates researchers to design selfoscillator frequency and locking range.Compared with traditional self-oscillation criteria,the analytical model proposed is more suitable for injection-locked CML-DFF dividers.Moreover,we proposed a new method of tuning frequency in this dissertation.The resistor load and inductive load CML-DFF divider have great advantages in power consumption and locking range.In the research of multi-mode frequency divider(MMD),the retime technology is adopted in order to optimize the time sequence.The measurement results show that in the fractional mode,the in-band phase noise performance could be optimized.Based on methods proposed in this dissertation,a K-band fractional-N frequency synthesizer is proposed.The measured results meet the desired requirement,such as output amplitude,spur and phase noise performance.Moreover,the chip can work from 125? to-45?.