Design Of Frequency Synthesizer System And Parts Of Key Modules

Based on charted semiconductor 0.35μm RF CMOS process, aΔ-ΣFractional-N Frequency Synthesizer has been designed. First of all, the basic structure and the influence of individual module on the whole system were analyzed in detail from a top level perspective. The effect of each noise source to the final output phase noise, the influence of Loop Filter (LPF) structure and Voltage Controlled Oscillator (VCO) gain on phase noise and chip area were chiefly researched in Matlab environment. Then, according to the design requirement, structures of each functional module were built, and detailed design was completed including Loop Filter (LPF), Charge Pump and Divider. The loop bandwidth and other loop parameters were balanced and optimized. Besides, the paper also studied the methods of how to design a CML (Current Mode Logic) divider and how to choose appropriate device parameters, which greatly simplified the circuit design. Finally, instantaneous features and Phase Noise features were obtained respectively by using Matlab for behavioral-level and SpectreRF for circuit-level. The comparison between these different levels showed that they were generally the same.The results of simulation showed that the Frequency Synthesizer had a tuning range of 1800MHz to 1930MHz with a phase noise of less than -120dBc/Hz at frequency offset of 900 KHz, and the simulated settling time is less than 350μs.