Design Of Key Modules In Frequency Synthesizer

Frequency synthesizer is the key module in transceiver system, used to provide stable local oscillation signals. In this paper, a phase and frequency detector (PFD), a charge pump (CP) and a programmable divider which are key modules in phase-locked loop (PLL) frequency synthesizer are analyzed and designed. The basic principle, research status and implementation techniques of the frequency synthesizer are introduced firstly. Secondly, the system structure is confirmed for charge pump phase-locked loop (CPPLL) integer-N frequency synthesizer. Finally, the theoretical analysis, design and simulation of several key modules are introduced.In this paper, the structure of edge triggered PFD is used. By selecting the TSPC structure D flip-flop, optimizing the gate circuit and designing the delay element, the PFD has a low power consumption and simple structure, and can maintain a wide range of phase with no dead zone. The CP based on error operational amplifier is proposed in this paper. Choosing the position of the MOS switch and the use of a current source to provide charging and discharging current reduce the current mismatch, and choosing the operating current reduces the phase noise caused by the charge pump.A programmable frequency divider based on pulse-swallow type integer programmable divider structure is proposed in this paper. CML structure is used in the D flip-flop of the synchronous 4/5 frequency divider in the 16/17 dual modulus divider, and TSPC structure is used in the D flip-flop of asynchronous 4 frequency divider, so that the dual modulus divider can meet the requirements of high frequency and low power consumption. The optimized design of bandwidth expansion of 16/17 dual modulus divider makes the maximum operating frequency of the programmable divider 8.8GHz or so.In this paper, design and chip are based on TSMC 0.13μm CMOS technology. The results of simulation show that:under 1.2V supply voltage, PFD’s phase range is (-1.99π,1.99π) with no dead zone; The working current of CP can be adjusted between 100 to 700μA, and output voltage within(0.2V,1.1V) range, current mismatch is less than 0.047%, and the phase margin is greater than 60 °; The programmable frequency divider can achieve the highest operating frequency of 8.8GHz, and it can achieve the division ratio of 256 to 4334 in the range when the reference frequency is from 2MHz to20MHz.