Chip Design, Design For Testability,

As the complexity of Integrated Circuit design and process is improving, the IC's test is Becoming more and more difficulty, Design for test (DFT) technology has become the main method to resolve the issue of chip test.The coming of System-on-chip (SoC) era makes the test problem more severe,and puts forward new requirement for the DFT methodology and IC's design flow.In this paper, the conventional test method is briefly elucidated, as well as fault mechanism, fault model and some standard related IC test. Then some popular DFT methodology is Summarized such as scan chain insertion, Built-in Self Test (BIST) and boundary scan method. The following content is to research how to realize OR1200 chip's design for testability based on analysis some DFT technology's characteristic and OR 1200 chip's circuit structure. Furthermore, Automatic Test Pattern Generation (ATPG) is used to verify the validity of DFT method. The result shows that this method can meet the test requirement.CMOS device dimensions have been down to the very deep submicrometer. Integrated ciructs are going toward higher density,higher speed and lower power dissipation, making new challenges on IC test and design for test. The challenges of test and design for testability are analyzed, Then discusses test and design for testability in SOC design .Furthermore, progress in test and design for testability is to looked forward.To solve the large size SOC test problems, the modeling of Sytem-On-a-Chip (SOC) test optimization has been formulated with different precedence, resource and core constraints.Then,a neural network for SOC test scheduling is presented,moreover, a neural network combined with heuristic algorithm has been developed to solve the large size SOC test problems.As demonstrated by the results that computer implement,the developed method can not only solve the large size SOC test problems, but is also capable of finding the optimal solutions within reasonable computing time. As the result shows, it has good performance in solving SOC test scheduling problems.