SoC Testability Design Based On Cortex-M

With the increasing complexity of chip design and the emergence of system on chip(So C),new challenges have been posed to the design and testing of So Cs.How to efficiently test and reduce testing costs has become a hot topic in So C design and testing.Design for testability techniques,by incorporating additional logic circuits during the design,can effectively enhance So C testing efficiency and reduce chip testing costs.To improve the controllability and observability of sequential circuits in Cortex-M3 based So C chips,scan testability design was applied by performing logic synthesis and completing automatic test pattern generation and logic equivalence check.The logic synthesis results met the expected constraints and the scan testability design achieved fault coverage of 96.23%.To improve the efficiency and quality of memory testing in So Cs,a flexible and scalable programmable memory built-in self-test(PMBIST)structure was utilized.It is compatible with four March series testing algorithms and can effectively meet the diverse testing requirements of internal memories in various environments,enhancing overall testing quality.The boundary scan testing technique based on the IEEE 1149.1 standard has been applied to address the interconnection issues of So C chips I/O pin and application in board level systems in this paper.The generation and validation of the boundary scan testing logic have been completed,and the correctness of the external testing,bypass,and shift/capture instructions specified in the IEEE 1149.1 standard has been verified.