Digital High-definition Television Channel Received The Program The Chip

Being a product integrating the most advanced image compression encoding technology and digital communication technology, digital HDTV becomes one of the focuses in high-technology competitions. Due to the great demand for HDTV receivers, ASICs for HDTV channel receiving will have a bright future in the world market.The great demand for electronic products stimulates the fast development of the IC industry. Being the fundation of the IC industry, semiconductor technology experiences drastic evolution. In the VDSM (very deep sub-micron) era, the continuous scaling of transistor feature size and the continuous growing of design size and its complexity has brought many serious problems and great challenges to ASIC designs.In this paper, many important aspects related to VDSM ASIC designs and their design flows and design methodology are discussed in great details. Their applications in the HDTV channel receiving chip are also presented.For VDSM ASIC designs, Logic synthesis, which is a bridge between logic design phase and physical design phase, should be more efficient and produce high quality of results at the same time. To reach the above requirements, a careful HDL coding style guidelines, a suitable delay estimation methods and a wise logic sythesis strategy become necessities. In order to cope with the problems brought by VDSM, all steps in the layout design flow, such as floorplanning, place and route, should be aware of all possible pitfalls. All the aspects mentioned above are discussed in this paper and their applications in the HDTV channel receiving chip has been demonstrated to be successful.Other indispensable ASIC design techniques, such as DFT (Design for Test) and static verification are also discussed in detail. In the project of HDTV channel receiving ASIC, DFT techniques based on scan-chains, STA (Static Timing Analysis) and formal verification has been adopted.