Full_custom Design Of Multi_threaded Parallel Integer Register File

Since the birth of the microprocessor, register file as a key component of its core, always requires a fast read and write access speed; and with the high-end microprocessors developing toward multi-thread and register window technology, register file must also support these technologies, so it has been a problem of current research to carry out a register which has multi-thread in parallel to high-speed read and write. The X microprocessor is a 64-bit multicore multithreading high-performance microprocessor, and it's Integer Register File which is the key point of the design needs high frequency, large scale and multi-port. Considering the speed of half-custom design based on standard cell is hard to meet the requests, the full-costom design method is chosen. The design and realization of the high-speed Register File has important signification to theory research and high value to project practicality.In this paper, a high-speed, supporting multi-theaded parallel Integer Register File is implemented in 65nm CMOS proces, it has 3-read ports and 2-write ports,128-words×72-bit. The typical simulation result indicates:read delay is less than 650ps, write delay is less than 580ps. Comparing with the; synthesis result of half-custom design based on standard cell, the accessing time reduced from 875ps to less than 580ps, which is optimized nearly 35%, and the area reduced from 130284μm2 to less than 106790μm2, which is optimized nearly 22%. They both achieve the design aim.The main contents of this paper include:To achieve supporting 4-thread in parallel, using two register window structure, the storage array uses some technologies including partition and bit line reuse to achieve the multi-thread storage structure, which supports for the X processor architecture.the circuit design of the high-speed register file is full-customed completed, which has reasonable improvement to make the circuit can be fast and effective work, morover the changes save a lot of area and power overhead, the measures which are the design of dynamic domino decoding circuit and single-ended sensitive amplifier and so on reduce not only the circuit size, but also the power consumption.completing the full-custom design of the layout of the Active window register file, optimizing the place of the layout to improve the circuit performance.