Research On Register File Management For The DSMT Architecture Based On EPIC

Parallelism extracting technology is an important method to improve the performance of microprocessors. EPIC, which can extract ILP in both software and hardware, is a more efficient art in ILP extracting follows superscalar and VILW. As it is more and more difficult to extract ILP due to the inherent relativity and parallelism in the program, new parallelism level, TLP(Thread Level Parallelism), is becoming the researching hotspot for the micro-architecture researchers. The DSMT architecture, which integrates dynamic threads extracting and threads switching mechanism into SMT architecture, is more powerful in parallelism extracting. EPIC expanding based on the DSMT architecture is a new meaningful attempt.Register file is one of the bottle-necks in SMT architecture. Multiple thread contexts result in large register file, but the increasing registers induce the problem of scaling area, ascending power consumption, increasing delay, etc. Hence, how to reduce the size of the register file without performance degrading comes to be a linchpin in SMT research.This thesis focuses on register file management for the DSMT architecture based on EPIC technology, and a register file management mechanism called SREN is proposed. In the SREN design, basically register renaming and RSE is combined and applied in VRM, which makes register allocation continuous in logic but discrete in physic. Then a "narrow oprand store aside" optimization is added based on the low bit-utilization of the register. Furthermore, it shorten the liveness of the register by allocates registers only if the oprand is ready based on the trait of the VRM structure, and it also de-allocates registers earlier by optimizes the compiler to cut the liveness of the register.SREN is simulated on a self-developed EDSMT simulator. The results show that the SREN structure can really reduce the need of the registers without performace degrading. The research of this paper benefits the future research work of SMT architecture based on EPIC.