Register File Design For Testability,

With the development of the deep sub-micron technology, the complexity of IC structure and function has increased and the size of the transistor has decreased, which makes testing technology a more and more hard issue for IC designer. Scientists and engineers have to pay more attention to the testability. Therefore, the discussion and research of DFT seems to be very significant.This paper focuses on the research of DFT about register file. The main work includes:Firstly, we systematically researched the popular DFT method and the design for testability of memory. And the characteristic of high-speed low-power register file has been further studied.Secondly, the programs and structure of testability for register file has been proposed. According to the characteristic of high-speed and small-volume, we adopt the mixed testing method with external incentives and BIST to design a test circuit for the high-speed low-power register file with 32words×32bits size. Internal High speed test coordinated with external low speed transmission of input and output makes at-speed test of register file available, thus reducing the difficulty of testing for high-speed register file. The design of the test circuit helps to the development of the field of testing.Thirdly, we explores and realizes the method and flow of mixed-signal simulation which is implemented between the test circuit designed with the classical digital design flow and the register file with full custom design. Related persons can take it as a reference for mixed-signal simulation.Finally, some specific problems and solutions during the realization process of the test circuit, such as front-end design, back-end physical layer and so on, have been introduced. The realization of the whole digital ASIC flow represents the common methods of digital IC design.