Radiation Hardened Design Of Register File In Microprocessor

Soft error caused by high energy particles is an important reliability problem in IC space applications.However,with the development of deep submicron technology,such as the continuous shrinking of device size,the decrease of power supply voltage and the improvement of operating speed,digital circuits are vulnerable to particle radiation even on the ground.Because CMOS circuit is more and more sensitive to soft errors caused by high energy particle collision,errors in register file may spread rapidly to different parts of the system,which leads to data corruption and application crash.Therefore,it is very important to protect the register file for reliable calculation of high-performance microprocessors.In addition,with the increase of the density of storage nodes,the probability of multiple bit upset(MBUs)of adjacent storage units increases.Because register file is located on the key path of processor pipeline,if the delay or power consumption is increased due to reliable design,it will affect the system performance and increase the power consumption of the system.Therefore,more optimized reliability design is neededFor the register file in microprocessor,this paper reinforces the register file according to the fact that a large part of the data value stored in the register is less than half of the register length.The data whose register value is less than half the length of the register is called short operator,and the data whose value is more than half of the register length is called long operand.The short operator copies data directly in the register,the long operands copy with the backup register,uses interleaved parity to detect multiple bit errors,and then uses the corresponding backup to correct the errors.The minimum system is built on OR1200 processor platform and the feasibility of the reinforcement method proposed in this paper is verified.The reliability of different number of backup registers is evaluated by using Simple Scalar simulator and Mibench Benchmark.The results show that using 8 registers as backup can achieve high reliability.The delay is lower than Hamming code and SEC?DED.Although the area and power consumption are higher than them,the correction ability of the proposed scheme can achieve the correction of any error of consecutive 4 bits.Compared with QBEC code with the same correction ability,the delay is reduced by 35.17%,the area is reduced by 5.73% and the power consumption is reduced by 9.63%.