High-performance, Low-power Soc Design And Register Stack Applications

IC design and microelectronics manufacturing has played a important role in our Information Industry. This thesis focuses on the realization of high-performance low-power register and its SoC integration.This paper mainly includes three aspects,First issue is the implementation of high-performance low-power register file. The main structure of register file includes storage unit, decoder, timing control module and the read out circuit. The paper of this paper presents a basic structure of a register file design by using full custom implementation to achieve the speed and lower power requirements.Second issue is the realization methods of SoC. The realization method of SoC is variety. Generally It is based on standard cell semi-custom design approach. In addition, it also can use full-custom design flow and FPGA design flow. They have advantages and disadvantages on different occasions for different applications.The last issue is the application of information security for heterogeneous multi-core design implementation issues. This paper focuses on the chip in the actual design of some specific problems encountered, such as a more accurate static timing analysis, clock crosstalk, power distribution, and substrate leakage, short channel effects and so on. The design of memory power consumption is already accounted for 40% of the entire design.The comparison between the full-custom design and the semi-custom design for register file design has been shown. It definitely proves that the full-custom design is much superior.