The Design And Realization Of PCI-Express2.0 PHY Based On Multiphase Clocks

The development of high-speed I/O bus impels the transfer from the conventional parallel I/O bus to the high-speed serial I/O bus, among which PCI Express is generally considered as the standard of next generation of I/O buses. So far according to the newest version 2.0 of PCI Express, the speed of serial data transport has been up to 5Gbps in each lane, which can satisfy almost all the ordinary requires in the industries.In this thesis, through the analysis and comparison of the prevailing architecture for high-speed Serializer and Deserializer (SerDes), certain unsuitability is thrown out under the condition of 0.13um ordinary process and finally a feasible method of PCIE physical (PHY) realization based on multiphase clocks is put forward. This method obviates the difficulties of hyper-speed clock generation and its rigorous demand toward circuit operation.Beyond that, in this thesis, the emphases are paid upon the detail realization of Charge Pump PLL (CPPLL) as the generator of multiphase clocks, which provides the premises of the whole PHY.The innovations and productions mainly include as below:1. A new realization architecture of PCIE PHY based on multiphase clocks is put forward and designed, at the same time the shift overflow of over-sampler was figured out when a circle shifter was added before the receiver using the cycle characteristic of clock.2. Design and realize a serializer for 5Gbps serial data transport in the custom-IC-design method.3. Comprehensively analyze the CPPLL working theory and the influence of its non-ideal situation, and then realize a custom design PLL which has 10 outputs at the frequency of 500MHz4. Summarize general design method and basic principle of mix signal layout.