Full Custom Design For Nanometer GHz CAM

The TLB on the critical path of microprocessor core contains data array and tag array. Data array is generally implemented by SRAM, while tag array is often realized by CAM. The CAM speeds up the virtual reality address translation of TLB through parallel and express matching, so the speed of CAM has great impact on microprocessor performance. The CAM designed by full-custom has the advantage of faster speed and smaller size, which is of important significance and suitable for various applications.The Main contribution and innovative points of this dissertation are given in the following:Structural design of dual match-line is optimized. Hierarchical match-line idea has been employed to the dual match-line structure, which results in faster match operation compared to that of original structure;Decoder design is optimized. The 6-64 decoder is implemented by two pre-decoded 3-8 decoders. The 6-64 decoder drives two sides wordlines by separating wordline to balance wordline loads and improve the decoding speed;A high-speed CAM has been implemented by full-custom to meet the performance requirements of TLB. The read and write operation of address decoding of CAM are processed in the posedge edge of clock, while the testing read and writing data are operated in the negative of clock. The match operation is operated in the posedge of clock. The layout simulation results indicate that the delay of read operation is 688ps, write operation 645ps, and match operation 382ps at the worst cases. The layout area is 0.11mm2.We also investigate soft error tolerant technology of CAM cells in 65nm CMOS process. Two CAM cells have been proposed, which could tolerant of soft errors. And the simulation results reveal that all the injected pulses are masked powerfully.